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lupa 4000: 4 megapixel cmos image sensor cyil1sm4000aa cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05712 rev. *d revised september 18, 2009 features 2048 x 2048 active pixels 12 m x 12 m square pixels optical format: 24.6 mm x 24.6 mm monochrome or color digital output 15 fps frame rate at full resolution 2 on-chip 10-bit adcs random programmable windowing and sub-sampling modes full snapshot shutter binning (voltage averaging in x-direction) limited supplies: nominal 2.5v (some supplies require 3.3v) serial to parallel interface (spi) 0c to 60c operational temperature range 127-pin pga package power dissipation: < 200 mw applications intelligent traffic system high speed machine vision overview this document describe s the interfac ing and drivin g of the lupa 4000 image sensor. this 4 mega-pixel cmos active pixel sensor features synchronous shutter and a maximal frame rate of 15 fps in full resolution. the readout speed can be boosted by sub-sampling and windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double and multiple slope functionality. the sensor is used with one or two outputs. two on-chip 10-bit adcs are used to convert the analog data to a 10-bit digital word stream. the sensor uses a 3-wire spi. it is housed in a 127-pin ceramic pga package. this data sheet allows the user to develop a camera system based on the described timing and interfacing. the lupa 4000 is available in color and monochrome without the cover glass. for engineering samples, contact imagesensors@cypress.com . figure 1. lupa 4000 photo ordering information marketing part number description package cyil1sm4000aa-gdc mono with glass 127 pin pga cyil1sm4000aa-gdcn mono with glass, nitrogen filled CYIL1SM4000AA-GWC mono without glass cyil1sc4000aa-gdc color without glass cyil1sm4000-eval mono demo kit demo kit [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 2 of 31 specifications general specifications electro-optical specifications table 1. general specifications parameter specification active pixels 2048 (h) x 2048 (v) pixel size 12 m x 12 m pixel type 6 transistor pixel pixel rate 66 mhz using a 33 mhz system clock and one or two parallel outputs shutter type full snapshot shutter (integration during readout is possible) frame rate 15 fps at 4.0 mpixel (can be bo osted by sub sampling and windowing) master clock 33 mhz windowing (roi) randomly programmable roi read out read out windowed, flipped, mirrored, and sub-sampled read out possible; voltage averaging in the x-direction adc resolution 2 on-chip, 10 bit sensitivity 11.61 v/lux.s in the visible band only (180 lux=1 w/m 2 ) extended dynamic range 66 db (2000:1) in single slope op eration and up to 90 db in multiple slope operation table 2. electro-optical specifications parameter value conversion gain 13.5 uv/e - full well charge 27000e - sensitivity 2090 v.m 2 /w.s average white light fill factor 37.5% parasitic light sensitivity <1/5000 dark noise 21e - qe x ff 37% at 680 nm fpn <1.25% rms of output signal amplitude of 1v prnu <2.5% rms at 25% and 75% of output signal dark signal <140 mv/s at 21c noise electrons < 40e - s/n ratio 2000:1 at 66 db (single slope operation) mtf 64% power dissipation <200 mw (typical without adcs) [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 3 of 31 figure 2. spectral response curve for mono figure 3. spectral response curve for color figure 2 and figure 3 show the spectral response characteristic. the curve is measured directly on the pixels. it includes effects of non sensitive areas in the pixel such as interconnection lines. the sensor is light sensitive between 400 nm and 1000 nm. the p eak qe * ff is 37.5% approximately between 500 nm and 700 nm. in view of a fill-factor of 60%, the qe is thus larger than 60% betwe en 500 nm and 700 nm. 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 400 500 600 700 800 900 1000 wavelength [nm] spectral response [a/w] qe 10% qe 20% qe 25% qe 30% qe 40% [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 4 of 31 figure 4. photo-voltaic response curve figure 4 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron curve is independent of any parameters. the voltage to electrons co nversion gain is 13.5 v/e - . note that the upper part of the curve (near saturation) is actually a logarithmic response. 0 0.2 0.4 0.6 0.8 1 1.2 0 20000 40000 60000 80000 100000 120000 140000 #electrons output swing [v] [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 5 of 31 electrical specifications absolute maximum ratings exceeding the maximu m ratings may impair the us eful life of the device. recommended operating conditions the following specifications apply for v dd = +2.5v. boldface limits apply for t a =t min to t max , all other limits t a =+25c. table 3. absolute maximum ratings [1] symbol description min max units vdd core digital supply voltage -0.5 2.9 v voo output stage power supply -0.5 2.9 v vaa analog supply voltage -0.5 2.9 v va3 column readout module -0.5 4.0 v vpix pixel supply voltage -0.5 2.9 v vmem_l power supply memory el ement (low level) -0.5 2.9 v vmem_h power supply memory element (high level) -0.5 4.0 v vres power supply to the reset drivers -0.5 4.0 v vres_ds power supply to the multiple slope reset drivers -0.5 2.9 v vddd digital supply adc circuitry -0.5 2.9 v vdda analog supply adc circuitry -0.5 2.9 v i io dc supply current drain per pin, any single input or output -50 50 ma t l lead temperature (5 sec soldering) 350 c t a ambient temperature range 0 60 c esd: human body model and charged device model see note [2] table 4. recommended operating conditions symbol power supply min supply tolerance recommended supply voltage for optimal performance (v) max supply tolerance vdd core digital supply voltage -10% 2.5 +10% voo output stage power supply -10% 2.5 +10% vaa analog supply voltage -10% 2.5 +10% va3 column readout module -1% 3.3 +1% vpix pixel supply voltage -5% 2.6 +5% vmem_l power supply memory elem ent (low level) -5% 2.6 +5% vmem_h power supply memory element (high level) -5% 3.3 +5% vres power supply to the reset drivers -5% 3.5 +5% vres_ds power supply to the multiple slope reset drivers -5% 2.5 +5% vddd digital supply adc circuitry -10% 2.5 +10% vdda analog supply adc circuitry -5% 2.5 +5% vpre_l power supply for precharge off-state - 0.4v 0 0v notes 1. absolute ratings are those values be yond which damage to the device may occur. 2. the lupa 4000 complies with jesd22-a114 hbm class 0 and jesd22- c101 class i. it is recommended that extreme care be taken whi le handling these devices to avoid dam ages due to esd event. [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 6 of 31 sensor architecture a schematic drawing of the architecture is given in figure 5 . the image core consists of a pixel array, one x-addressing and two y-addressing registers (only one drawn), pixel array drivers and column amplifiers. the image sensor of 2048 x 2048 pixels is read out in progressive scan. one or two output amplifiers read out the image sensor. the output amplifiers are working at 66 mhz pixel rate nominal speed or each at 33 mhz pixel rate in case the two output amplifiers are used to read out the imager. the complete image sensor is designed for operation up to 66 mhz. the structure allows having a programmable addressing in the x-direction in steps of two and in the y-direction in steps of two (only even start addresses in x-direction and y-direction are possible). the starting point of the address is uploadable by means of the spi figure 5. block diagram of image sensor the 6t pixel to obtain the global shutter feature combined with a high sens itivity and good parasitic light sensitivity (pls), the pixel arc hitecture given in figure 6 is implemented. figure 6. 6t pixel architecture this pixel architecture is designed in a 12 m x 12 m pixel pitch. the pixel is designed to meet the specific ations described in table 1 and table 2 . column ampli?ers on chip drivers y shift register select drivers eos_y clk_y s ync_y 2 differential outputs eos_x reset, mem_hl, precharge, sample pixel array 2048 * 2048 xshiftregister sync_x clk_x logic blocks dac spi rese t vpix vmem row-selec t sampl e [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 7 of 31 frame rate and windowing frame rate to acquire a frame rate of 15 frames/sec, the output amplifier should run at 66 mhz pixel rate or two output amplifiers should run at 33 mhz each, assuming a row overhead time (rot) of 200 ns. the frame period of the lupa 4000 sensor is calculated as follows: frame period = fot + (nr. lines * (rot + pixel period * nr. pixels) with: fot: frame overhead time = 5 s. nr. lines: number of lines read out each frame (y). nr. pixels: number of pixels read out each line (x). rot: rot = 200 ns (nominal; can be further reduced). pixel period: 1/66 mhz = 15.15 ns. example read out of the full resolution at nominal speed (66 mhz pixel rate): frame period = 5 s + (2048 x (200 ns + 15.15 ns x 2048) = 64 ms 15 fps. roi readout (windowing) windowing is achieved by a spi in which the starting point of the x-address and y-address is up loaded. this downloaded starting point initiates the shift register in the x-direction and y-direction triggered by the sync_x and sy nc_y pulse. the minimum step size for the x-address and the y-address is 2 (only even start addresses can be chosen). the si ze of both address registers is 10-bits. for instance, when the addresses 0000000001 and 0000000001 are uploaded, the readout starts at line 2 and column 2. output amplifier the sensor has two output amplif iers. a single amplifier can be operated at 66 mpixels/sec to bring the whole pixel array of 2048 by 2048 pixels at the required frame rate to the outside world. the second output amplifier can be enabled in parallel if the clock frequency is decreased to 33 msamples/sec. using only one output-stage, the output signal is the result of multiplexing between the two internal buses. when using two output-stages, both outputs are in phase. each output-stage has two outputs. one output is the pixel signal; the second output is a dc signal which offset can be programmed using a 7-bit word. the dc signal is used for common mode rejection between the two signals. the disadvantage is an increase in power dissipation. however, this can be reduced by setting the highest dac voltage by means of the spi figure 7. output stage architecture. the output voltage of out1 is between 1.3v (dark level) and 0.3v (white level) and depends on process variations and voltage supply settings. the output voltag e of out2 is determined by the dac. table 5. frame rate as function of roi read out and sub sampling image resolution (x*y) frame rate [frames f/s] frame readout time [ms] comment 2048 x 2048 15 67 full resolution. 1024 x 2048 31 32 subsample in x-direction. 1024 x 1024 62 16 roi read out. 640 x 480 210 4.7 roi read out. out1: pixel signal out2: dc signal image sensor dac spi 7bits [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 8 of 31 pixel array drivers we have foreseen on this image sensor on-chip drivers for the pixel array signals. not only the driving on system level is easy and flexible, also the maximum currents applied to the sensor are controlled on chip. this means that the charging on sensor level is fixed and that the sensor cannot be overdriven from externally. the operation of the on-chip drivers is explained in detail in timing and readout of image sensor on page 13. column amplifiers the column amplifiers are designed for minimum power dissipation and minimum loss of signal; for this reason, multiple biasing signals are required. the column amplifiers also have the "voltage-averaging" feature integrated. in case of volt age averaging mode, the voltage average between two columns is taken and read out. in this mode only 2:1 pixels must be read out. to achieve the voltage-averaging mode, an additional external digital signal called "voltage-averaging" is required in combination with a bit from the spi. analog to digital converter the lupa 4000 has two 10-bit flash analog to digital converters running nominally at 10 msamples/s. the adc block is electrically separated from the image sensor. the inputs of the adc must be tied externally to the outputs of the output amplifiers. if the internal adc is not used, then the power supply pins to the adc and the i/os must be grounded. even in this configuration, th e internal adcs are not able to sustain the 66 mpixel/sec provi ded by the output amplifier when run at full speed. one adc samples the even columns and the other samples the odd columns. although the input range of the adc is between 1v and 2v and the output rang e of the analog signal is only between 0.3v and 1.3v, the analog output and digital input may be tied to each other directly. this is possible because there is an on-chip level-shifter located in front of the adc to lift up the analog signal to the adc range. adc timing the adc converts the pixel data on the falling edge of the adc_clock but it takes 2 clock cycles before this pixel data is at the output of the adc. th is pipeline delay is shown in figure 8 . figure 8. adc timing table 6. adc specifications parameter specification input range 1v - 2v [3] quantization 10 bits nominal data rate 10 msamples/s dnl (linear conversion mode) typ < 0.4 lsb rms inl (linear conversion mode) typ < 3.5 lsb input capacitance < 2 pf power dissipation at 33 mhz 50 mw conversion law linear/gamma-corrected 200 ns 100 ns note 3. the internal adc range is typ. 50 mv lower then the external applied adc_vhigh and adc_vlow voltages due to voltage drops ove r parasitic internal resistors in the adc. [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 9 of 31 setting the adc reference voltages figure 9. internal and external adc connections the internal resistor r adc has a value of approximately 300 . this value of this resistor is not te sted at sort or at final test. tweaking may be required as the recommended resistors in figure 9 are determined by trade-off between speed and power consumption. synchronous shutter in a synchronous (snapshot) shutter, light integration takes pla ce on all pixels in parallel although subsequent readout is seq uential. figure 10. synchronous shutter operation figure 10 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and read out cycle can occur in parallel or in sequential mode (see timing and readout of image sensor on page 13). resistor typical value ( ) r adc_vhigh 75 r adc 300 r adc_vlow 220 rhigh_adc 2.5v ref_low ~ 1 v ref_high ~ 2 v rlow_adc r adc externa l interna l externa l time axis line number integration time burst readout time common reset common sample&hold flash could occur here [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 10 of 31 non destructive readout (ndr) the sensor can also be read out in a non destructive way. after a pixel is initially reset, it can be read multiple times, without resetting. the initial reset level and all intermediate signals can be recorded. high light levels saturates the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, use the latest samples. figure 11. principle of ndr essentially an active pixel array is read multiple times and reset only once. the external system intelligence takes care of the interpretation of the data. ta b l e 7 summarizes the advantages and disadvantages of non-destructive readout. operation and signalling the different signals are classified into the following groups: power supplies and grounds biasing and analog signals pixel array signals digital signals test signals power supplies and ground every module on chip including co lumn amplifiers, output stages, digital modules, and drivers has its own power supply and ground. off chip, the grounds can be combined, but not all power supplies may be combined. this results in several different power supplies, but this is required to reduce electrical cross-talk and to improve shielding, dynamic range, and output swing. on chip, the ground lines of every module are kept separately to improve shielding and electrical cross talk between them. an overview of the supplies is given in table 8 and ta b l e 9 . ta b l e 9 summarizes the supplies related to the pixel array signals and table 8 summarizes the supplies related to all other modules time table 7. advantages and disadvantages of ndr advantages disadvantages low noise, because it is true cds. system memory required to record the reset level and the intermediate samples. high sensitivity, because the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range, because the results incl udes signal for short and long integrations times. requires system level digital calculations. table 8. power supplies name dc current max current typ description vaa 7 ma 50 ma 2.5v power supply column readout module. va3 10 ma 50 ma 3.3v power supply column readout module. should be tuneable to 3.3v max. vdd 1 ma 200 ma 2.5v power supply digital modules voo 20 ma 20 ma 2.5v power supply output stages vdda 1 ma 200 ma 2.5v analog supply of adc circuitry vddd 1 ma 200 ma 2.5v digital supply of adc circuitry [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 11 of 31 the maximum currents mentioned in ta b l e 8 and table 9 are peak currents which occur once per frame (except for vres_ds in multiple slope mode). all power supplies should be able to deliver these currents except for vmem_l and vpre_l, which must be able to sink this current. the maximum peak current for vpix should not be higher than 500 ma. it is important to notice that no power supply filtering on chip is implemented and that noise on these power supplies can contribute immediately to the noise on the signal. the voltage supplies vpix and vaa must be noise free. startup sequence the lupa 4000 goes in latch up (draw high current) as soon as all power supplies are turned on at the same time. the sensor comes out of latch up and starts working normally as soon as it is clocked. a power supply with a 400 ma limit is recommended to avoid damage to the sensor. it is recommended to avoid the time that the device is in the latch up state, so clocking of the sensor should start as soon as the system is turned on. to completely avoid latch up of the image sensor, the following sequence should be taken into account: 1. apply vdd 2. apply clocks and digital pulses to the sensor to count 1024 clock_x and 2048 clock_y pulses to empty the shift registers 3. apply other supplies biasing and analog signals the analog output levels that may be expected are between 0.3v for a white, saturated, pixel and 1.3v for a black pixel. two output stages are foreseen, each consisting of two output amplifiers, resulting in four output s. one output amplifier is used for the analog signal resulting from the pixels. the second amplifier is used for a dc reference signal. the dc level from the buffer is defined by a dac, which is controlled by a 7-bit word downloaded in the spi. additionally, an extra bit in the spi defines if one or two output stages are used. ta b l e 1 0 summarizes the biasing signals required to drive this image sensor. to optimize biasing of column amplifiers to power dissipation, several biasing resistors are required. this optimisation results in an increase of signal swing and dynamic range. table 9. power supplies related to pixel signals name dc current max current typ description vres 1 ma 200 ma 3.5v power supply reset drivers. vres_ds 1 ma 200 ma 2.5v power supply dual slope reset drivers. vmem_h 1 ma 200 ma 3.3v power supply memory elements in pixel for high voltage level vmem_l 1 ma 200 ma 2.6v power supply memory elements in pixel for low voltage level. should be tuneable vdd 1 ma 200 ma 2.5v core digital supply voltage vpix 12 ma 500 ma 2.5v power supply pixel array vpre_l 1 ma 200 ma 0v power supply for precharge in off-state. this pin may be connected to ground. table 10. overview of bias signals signal comment related module dc level out_load connect with 60 k to voo and capacitor of 100 nf to gnd output stage 0.7 v dec_x_load connect with 2 m to vdd and capacitor of 100 nf to gnd x-addressing 0.4 v muxbus_load connect with 25 k to vaa and capacitor of 100 nf to gnd multiplex bus 0.8 v nsf_load connect with 5 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load_fast connect with 10 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v pre_load connect with 3 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.4 v col_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v dec_y_load connect with 2 m to vdd and capacitor of 100 nf to gnd y-addressing 0.4 v psf_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v precharge_bias connect with 1k to vdd and capacitor of at least 200 nf to gnd pixel drivers 1.4v [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 12 of 31 each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation. some modules have two biasing resistors: one to achieve the high speed and another to minimize power dissipation. pixel array signals the pixel array of the image sensor requires digital control signals and several different power supplies. this section explains the relation between the control signals and the applied supplies and the internal generated pixel array signals. figure 12 illustrates that the internal generated pixel array signals are reset, sample, pr echarge, vmem, and row_select. these are internal generated signa ls derived by on-chip drivers from external applied signals. row_select is generated by the y addressing and is not be discussed in this section. the function of each of the signals is: reset: resets the pixel and initiates the integration time. if reset is high, then the photodiode is forced to a certain voltage. this depends on vpix (pixel supply) and the high level of reset signal. the higher these signals or supplies, the higher the voltage-swing. the limitation on the high level of reset and vpix is 3.3v. nevertheless, there is no use increasing vpix without increasing the reset level. the opposite is true. additionally, it is this reset pulse that also cont rols the dual or multiple slope feature inside the pixel. by giving a reset pulse during integration, but not at full reset level, the photodiode is reset to a new value, only if this value is sufficient decreased due to light illumination. the low level of reset is 0v, but the high level is 2.5v or higher (3.3v) for the normal reset and a lower (<2.5v) level for the multiple slope reset. precharge: precharge serves as a load for the first source follower in the pixel and is activated to overwrite the current information on the storage node by the new information on the photodiode. precharge is controlled by an external digital signal between 0 and 2.5v. sample: samples the photodiode information onto the memory element. this signal is also a standard digital level between 0 and 2.5v. vmem: this signal increases the information on the memory element with a certain offset. this increases the output voltage variation. vmem changes between vmem_l (2.5v) and vmem_h (3.3v). figure 12. internal timing of pixel (levels are defined by the pixel array voltage supplies; for correct polarities of the signals refer to table 11 ) the signals in figure 12 are generated from the on-chip drivers. these on-chip drivers need two types of signals to generate the exact type of signal. it needs digital control signals between 0 and 3.3v (internally converte d to 2.5v) with normal driving capability and power supplies. the control signals are required to indicate the moment they need to occur and the power supplies indicate the level. vmem is made of a control signal mem_hl and 2 supplies vmem_h and vmem_l. if the signal mem_hl is the logic ?0? than the internal signal vmem is low, if mem_hl is logic ?1? the internal signal vmem is high. reset is made by means of two control signals: reset and reset_ds and two supplies: vres and vres_ds. depending on the signal that becomes active, the corresponding supply level is applied to the pixel. ta b l e 11 summarizes the relation between the internal and external pixel array signals. table 11. overview of internal and external pixel array signals internal signal vlow vhigh external control signal low dc level high dc level precharge 0 0.45v precharge (al) vpre_l controlled by bias-resistor sample 0 2.5v sample (al) gnd vdd reset 0 2.5 to 3.3v reset (ah) and reset_ds (ah) gnd vres and vres_ds vmem 2.0 to 2.5v 2.5 to 3. 3v mem_hl (al) vmem_l vmem_h [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 13 of 31 in case the dual slope operation is desired, you need to give a second reset pulse to a lower reset level during integration. this is done by the control signal reset_ds and by the power supply vres_ds that defines the level to which the pixel has to be reset. note that reset is dominant ov er reset_ds, which means that the high voltage level is applied for reset, if both pulses occur at the same time. note that multiple slopes are possible having multiple reset_ds pulses with a lower vres_ds level for each pulse given within the same integration time the rise and fall times of the internal generated signals are not very fast (200 ns). in fact they are made rat her slow to limit the maximum current through the power supply lines (vmem_h, vmem_l, vres, vres_ds, vdd). current limitation of those power supplies is not required. nevertheless, it is advisable to limit the currents not higher than 400 ma. the power supply vmem_l must be able to sink this current because it must be able to discharge the internal capacitance from the level vmem_h to the leve l vmem_l. the external control signals should be capable of driving input capacitance of about 10 pf. digital signals the digital signals control the readout of the image sensor. these signals are: sync_y (ah [4] ): starts the readout of the frame. this pulse synchronises the y-address register: active high. this signal is at the same time the end of th e frame or window and determines the window width. clock_y (ah [4] ): clock of the y-registe r. on the rising edge of this clock, the next line is selected. sync_x (ah [4] ): starts the readout of the selected line at the address defined by the x-address register. this pulse synchronises the x-address register: active high. this signal is at the same time the end of the line and determines the window length. clock_x (ah [4] ): determines the pixel rate. a clock of 33 mhz is required to achieve a pixel rate of 66mhz. spi_data (ah [4] ): the data for the spi. spi_clock (ah [4] ): clock of the spi. this clock downloads the data into the spi register. spi_load (ah [4] ): when the spi register is uploaded, then the data is internally available on the rising edge of spi_load. sh_kol (al [5] ): control signal of the column readout. is used in sample and hold mode and in binning mode. norowsel (ah [4] ): control signal of the column readout. (see timing and readout of image sensor ). pre_col (al [5] ): control signal of the column readout to reduce row blanking time. voltage averaging (ah [4] ): signal required obtaining voltage averaging of 2 pixels. test signals the test structures implemen ted in this image sensor are: array of pixels (6*12) which ou tputs are tied together: used for spectral response measurement. temperature diode (2): apply a forward current of 10 a to 100 a and measure the voltage v t of the diode. v t varies linear with the temperature (v t decreases with approximately 1.6 mv/c). end of scan pulses (do not use to trigger other signals): ? eos_x: end of scan signal: is an output signal, indicating when the end of the line is reac hed. is not generated when doing windowing. ? eos_y: end of scan signal: is an output signal, indicating when the end of the frame is reached . is not generated when doing windowing. ? eos_spi: output signal of the spi to check if the data is transferred correctly through the spi. timing and readout of image sensor the timing of the lupa 4000 sensor consists of two parts. the first part is related to the control of the pixels, the integration time, and the signal level. the second part is related to the readout of the image sensor. as full synchronous shutter is possible with this image sensor, integration time and readout can be in parallel or sequential. in the parallel mode the integrat ion time of the frame i is ongoing during readout of frame i-1. figure 13 shows this parallel timing structure figure 13. integration and readout in parallel notes 4. ah: active high 5. al: active low i ntegration i + 2 r ead frame i + 1 i ntegration i + 1 r ead frame i [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 14 of 31 the control of the frame?s re adout and integration time are independent of each other with the only exception that the end of the integration time from frame i+1 is the beginning of the readout of frame i+1. the lupa 4000 sensor is also used in sequential mode (triggered snapshot mode) wh ere readout and integration is sequential. figure 14 shows this sequential timing. figure 14. integration and readout in sequence timing of pixel array the first part of the timing is re lated to the timing of the pixel array. this implies control of integration time, synchronous shutter operation, and sampling of the pixel information onto the memory element inside each pixel. the signals required for this control are described in pixel array signals and in figure 12 . figure 15 shows the external applied signals required to control the pixel array. at the end of th e integration time from frame i+1, the signals mem_hl, precharge, and sample must be given. the reset signal controls the integrat ion time, which is defined as the time between the falling edge of reset and the rising edge of sample. figure 15. pixel array timing (the integration time is determined by the falling edge of the reset pulse. the longer the pulse is high, the shorter the integration time. at the end of the inte gration time, the information has to be stored onto the memory element for readout.) timing specifications for each signal are shown in table 12 . falling edge of precharge is equal or later than falling edge of vmem. sample is overlapping with precharge. rising edge of vmem is more than 200 ns after rising edge of sample. rising edge of reset is equal or later than rising edge of vmem. i ntegration i + 1 r ead frame i + 1 i ntegration i r ead frame i table 12. timing specifications symbol name value a mem_hl 5 - 8.2 s b precharge 3 - 6 s c sample 5 - 8 s d precharge-sample > 2 s e integration time > 1 s [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 15 of 31 the timing of the pixel array is straightforward. before the frame is read, the information on th e photodiode must be stored onto the memory element inside the pixels. this is done with the signals mem_hl, precharge, and sample. when precharge is activated, it serves as a load fo r the first source follower in the pixel. sample stores the phot odiode information onto the memory element. mem_hl pumps up this value to reduce the loss of signal in the pixel and this signal must be the envelop of precharge and sample. after mem_hl is high again, the readout of the pixel array starts. the frame blanking time or frame overhead time is thus the time t hat mem_hl is low, which is about 5 s. after the readout starts, the photodiodes can all be initialised by reset for the next integration time. the minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. keeping the slow fall times of the corresponding internal generated signals in mind, the minimal integration time is about 2 s. an additional reset pulse of minimum 2 s can be given during integration by asserting reset_ds to implement the double slope integration mode. readout of image sensor as soon as the information of the pixels is stored in to the memory element of each pixel, it can be readout sequentially. integration and readout can also be done in parallel. the readout timing is straightforward and is basically controlled by sync and clock pulses. figure 16 shows the top level concept of this timing. the readout of a frame consists of the fram e overhead time, the selection of the lines sequentially, and the readout of the pixels of the selected line. figure 16. readout of image sensor (f.o.t: frame overhead time. r.o.t: row overhead ti me. l: selection of line, c: selection of column) the readout of an image consis ts of the fot (frame overhead time) and the sequential selection of all pixels. the fot is the overhead time between two frames to transfer the information on the photodiode to the memory elements. figure 15 shows that at this time mem_hl is low (typically 5 s). after the fot, the information is stored into the memory elements and a sequential selection of rows and columns makes sure the frame is read. x and y addressing to readout a frame the lines are selected sequentially. figure 17 gives the timing to select the lines sequentially. this is done with a clock_y and sync_y signal. the sync_y signals synchronises the y-addressing and initialises t he y-address selection registers. the start address is the address downloaded in the spi multiplied by two. on the rising edge of clock_y the next line is selected. the sync_y signal is dominant and from the moment it occurs the y-address registers are initialised. if a sync_y pulse is given before the end of the frame is reac hed, only a part of the frame is read. to obtain a correct initialisation, sync_y must contain at least one rising edge of clock_y when it is active. r eadout pixels r .o.t r eadout lines l 2048 l 3 l 2 f .o.t i ntegration i + 2 r ead frame i l 1 c1 c2 c2048 [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 16 of 31 figure 17. x and y addressing as soon as a new line is selected, it must be read out by the output amplifiers. before the pi xels of the selected line can be multiplexed onto the output amplifiers, wait for a certain time, indicated as the rot or row overhead time shown in figure 17 . this is the time to get the data stable from the pixels to the output bus before the output stages. this rot is in fact lost time and rather critical in a high speed sensor. different timings to reduce this rot are explained later in this section. during the selection of one line, 2048 pixels are selected. these 2048 pixels must be read out by one (or two) output amplifier. note that the pixel rate is t he double frequency of the clock_x frequency. to obtain a pixel rate of 66 mhz, apply a pixel clock clock_x of 33mhz. when only one analog output is used, two pixels are output every clock_ x period. when clock_x is high, the first pixel is selected; when clock_x is low, the next pixel is selected. consequently, during one complete period of clock_x two pixels are read out by the output amplifier. if two analog outputs are used each clock-x period one pixel is presented at each output. table 13. readout timing specifications symbol name value a sync_y >20 ns b sync_y-clock_y >0 ns c clock_y-sync_y >0 ns d norowsel >50 ns e pre_col >50 ns f sh_col 200 ns g voltage averaging >20 ns h sync_x-clock_x >0 ns [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 17 of 31 figure 18. x-addressing clock_x, sync_x, internal selection pixe l 1 and 2, internal selection pixel 3 an d 4, internal selection pixel 5 and 6 the first pixel selected is the x-address downloaded in the spi. the starting address is the number downloaded into the spi, multiplied with 2. windowing is achieved by a starting address downloaded in the spi and the size of the window. in the x-direction, the size is determined by the moment a new clock_y is given. in the y-direction, the sync_y pulse determines the size. the best way to obtain a certain window is by using an internal counter in the controller. figure 18 is the simulation result after extraction of the layout module from a different sensor to show the principle. in this figure the pixel clock has a frequency of 50 mhz, which results in a pixel rate of 100 msamples/sec. figure 19 shows the relation between the applied clock_x and the output signal. [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 18 of 31 figure 19. output signal related to clock_x signal from bottom to top: clock_x, sync_x and output. output level before the first pixel is the level of the last pixel on previous line as soon as sync_x is high and one rising edge of clock_x occurs, the pixels are brought to the analog outputs. this is again the simulation result of a comparable sensor to show the principle. note the time difference between the clock edge and the moment the data is seen at the output. as this time difference is very difficult to predict in advance, it is advisable to have the adc sampling clock flexible to set an optimal add sampling point. the time differences can easily vary between 5 ns and 15 ns and must be tested on the real devices. reduced rot timing the row overhead time is the time between the selection of lines that you must wait to get the da ta stable at the column amplifiers. it is a loss in time, which should be reduced as much as possible. output 1 sync_x clock_x: 25mhz p ixel 1 pixel2.: pixel period : 20nsec dark s aturated [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 19 of 31 standard timing (200 ns) figure 20. standard timing for the rot only pre_col and norowsel control signals are required in this case, the control signals norowsel and pre_col are made active for about 20 ns from the moment the next line is selected. the time these pulses must be active is related to the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel and pre_col may be. after these pulses are given, wait for at l east 180 ns before the first pixel is sampled. for this mode sh_col must be made active (low) all the time. backup timing (rot =100-200 ns) a straightforward way of reducing the rot is by using a sample and hold function. by means of sh_col the analog da ta is tracked during the first 100 ns during the selection of a new set of lines. after 100 ns, the analog data is stored. the rot is in this case reduced to 100 ns, but as the internal data is no t stable yet, dynamic range is lost because not the complete analog levels are reached yet after 100 ns. figure 21 shows this principle. sh_col is now a pulse of 100 ns-200 ns starting at the same moment as pre_col and norowsel. the duration of sh_col is equal to the rot. the shorter this time the shorter the rot; however, this also lowers the dynamic range. in case "voltage averaging" is required, the sensor must work in this mode with sh_col signal and a "voltage averaging" signal must be generated after sh_col drops and before the readout starts (see figure 17 ) figure 21. reduced standard rot with sh_col signal pre_col (short pulse), norowsel (sho rt pulse) and sh_col (large pulse) precharging the buses this timing mode is exactly the same as the mode without sample and hold, except that the prebus1 and prebus2 signals are activated. note that precharging of the buses can be combined with all of the timing modes discussed earlier. the idea is to have a short pulse of about 5 ns to precharge the output buses to a well known level. this mode makes the ghosting of bad columns impossible. in this mode, nsf_load must be made much larger (at least 1 m ). [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 20 of 31 figure 22. x and y addressing with precharging of the buses table 14. readout timing specifications with precharching of the buses symbol name value a sync_y >20 ns b sync_y-clock_y >0 ns c clock_y-sync_y >0 ns d norowsel >50 ns e pre_col >50 ns f sh_col 200 ns (or cst low, depending on timing mode) g voltage averaging >20 ns h sync_x-clock_x >0 ns i prebus pulse as short as possible [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 21 of 31 serial-parallel-interface (spi) the spi is required to upload the different modes. table 15 shows the parameters and their bit position when all zeros are loaded into the spi, the sensor starts at pixel 0,0. the scanning is from left to right and from top to bottom. there is no sub sampling or voltage averaging and only one output is used. the dac has the lowest level at its output. when using sub sampling, only even x-addresses may be applied. figure 23. spi block diagram and timing table 15. spi parameters parameter bit # remarks y-direction 0 1: from bottom to top y-address 1-10 bit 1 is lsb x-voltage averaging enable 11 1: enabled x-subsampling 12 1: subsampling x-direction 13 0: from left to right x-address 14-23 bit 14 is lsb nr output amplifiers 24 0: 1 output dac 25-31 bit 25 is lsb d q c d q c spi_in to sensor clock_spi load_addr 32 outputs to sensor clock_spi spi_in unity ce ll e ntire uploadable block load_addr b0 b1 b2 b31 load_addr clock_spi spi_in command applied to sensor bit 0 bit 31 [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 22 of 31 pin list ta b l e 1 6 is a list of all the pins and their functionalities. table 16. pin list [6, 7, 8] pad pin pin name pin type description 1 e1 sync_x input digital input. synchronises the x-address register. 2 f1 eos_x testpin indicates when the end of the line is reached. 3 d2 vdd supply power supply digital modules. 4 g2 clock_x input digital input. determines the pixel rate. 5 g1 eos_spi testpin checks if the data is transferred correctly through the spi. 6 f2 spi_data input digital input. data for the spi. 7 h1 spi_load input digital input. loads data into the spi. 8 h2 spi_clock input digital input. clock for the spi. 9 j2 gndo ground ground output stages 10 j1 out2 output analog output 2. 11 k1 out2dc output reference output 2. 12 m2 voo supply power supply output stages 13 l1 out1dc output reference output 1. 14 m1 out1 output analog output 1. 15 n2 gndo ground ground output stages. 16 p1 vaa supply power supply analog modules. 17 p2 gnda ground ground analog modules. 18 n1 va3 supply power supply column modules. 19 p3 vpix supply power supply pixel array. 20 q1 psf_load input analog reference input. biasi ng for column modules. connect with r=1 m to vaa and decouple with c=100 nf to gnda. 21 q2 nsf_load input analog reference input. bi asing for column modules. connect with r=5 k to vaa and decouple with c=100 nf to gnda. 22 r1 muxbus_load input analog reference input. biasing for multiplex bus. connect with r=25 k to vaa and decouple with c=100 nf to gnda. 23 r2 uni_load_fast input analog reference input. bias ing for column modules. connect with r=10 k to vaa and decouple with c=100 nf to gnda. 24 q3 pre_load input analog reference input. bias ing for column modules. connect with r=3 k to vaa and decouple with c=100 nf to gnda. 25 q4 out_load input analog reference input. bias ing for output stage. connect with r=60 k to vaa and decouple with c=100 nf to gnda. 26 n3 dec_x_load input analog reference input. bias ing for x-addressing. connect with r=2 m to vdd and decouple with c=100 nf to gndd. 27 q5 uni_load input analog reference input. biasing for column modules. connect with r=1 m to vaa and decouple with c=100 nf to gnda. 28 q6 col_load input analog reference input. biasi ng for column modules. connect with r=1 m to vaa and decouple with c=100 nf to gnda. 29 q7 dec_y_load input analog reference input. bias ing for y-addressing. connect with r=2 m to vdd and decouple with c=100 nf to gndd. 30 r3 vdd supply power supply digital modules. 31 m3 gndd ground ground digital modules. 32 l2 prebus1 input digital input. control signal to reduce readout time. [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 23 of 31 33 l3 prebus2 input digital input. control signal to reduce readout time. 34 q8 sh_col input digital input. contr ol signal of the column readout. 35 r4 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 36 r5 norowsel input digital input. contr ol signal of the column readout. 37 r6 clock_y input digital input. clock of the y-addressing. 38 r7 sync_y input digital input. synchronises the y-address register. 39 k2 eos_y_r testpin indicates when the end of fr ame is reached when scanning in the 'right' direction. 40 q9 temp_diode_p testpin anode of temperature diode. 41 q10 temp_diode_n testpin cathode of temperature diode. 42 r8 vpix supply power supply pixel array. 43 r9 vmem_l supply power supply vmem drivers. 44 r10 vmem_h supply power supply vmem drivers. 45 r11 vres supply power supply reset drivers. 46 q11 vres_ds supply power supply reset drivers. 47 r12 adc1_ref_low input analog reference input . low reference voltage of adc (see figure 9 for exact resistor value). 48 q12 adc1_linear_conv input digital input. 0= linear conversion; 1= gamma correction. 49 p15 adc1_bit_9 output digital output 1 <9> (msb). 50 q14 adc1_bit_8 output digital output 1 <8>. 51 q15 adc1_bit_7 output digital output 1 <7>. 52 r13 adc1_bit_6 output digital output 1 <6>. 53 r14 adc1_bit_5 output digital output 1 <5>. 54 r15 adc1_bit_4 output digital output 1 <4>. 55 p14 adc1_bit_3 output digital output 1 <3>. 56 q13 adc1_bit_2 output digital output 1 <2>. 57 r16 adc1_bit_1 output digital output 1 <1>. 58 q16 adc1_bit_0 output digital output 1 <0> (lsb). 59 p16 adc1_clock input adc clock input. 60 n14 adc1_gndd supply digital gnd of adc circuitry. 61 n15 adc1_vddd supply digital supply of adc circuitry (nominal 2.5v). 62 l16 adc1_gnda supply analog gnd of adc circuitry. 63 l15 adc1_vdda supply analog supply of adc circuitry (nominal 2.5v). 64 n16 adc1_bit_inv input digital input. 0=no inversion of output bits; 1 = inversion of output bits. 65 m16 adc1_cmd_ss input analog reference input. biasing of second stage of adc. connect to v dda with r=50 k and decouple with c=100 nf to gnda. 66 l14 adc1_nalog_in input analog input of first adc. 67 m15 adc1_cmd_fs input analog reference input. b iasing of first stage of adc. connect to v dda with r=50 k and decouple with c=100 nf to gnda. 68 m14 adc1_ref_high input analog reference input. high reference voltage of adc. (see figure 9 for exact resistor value) 69 k14 vres_ds supply power supply reset drivers. 70 j14 vres supply power supply reset drivers. table 16. pin list [6, 7, 8] (continued) pad pin pin name pin type description [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 24 of 31 71 j15 vpre_l supply power supply precharge drivers. must be able to sink current. can also be connected to ground. 72 j16 vdd supply power supply digital modules. 73 k15 vmem_h supply power supply vmem drivers. 74 k16 vmem_l supply power supply vmem drivers. 75 h15 adc2_ref_low input analog reference input. low reference voltage of adc. (see figure 9 for exact resistor value) 76 h16 adc2_linear_conv input digital input. 0= linear conversion; 1= gamma correction. 77 g16 adc2_bit_9 output digital output 2 <9> (msb). 78 f16 adc2_bit_8 output digital output 2 <8>. 79 e16 adc2_bit_7 output digital output 2 <7>. 80 g15 adc2_bit_6 output digital output 2 <6>. 81 g14 adc2_bit_5 output digital output 2 <5>. 82 f14 adc2_bit_4 output digital output 2 <4>. 83 e14 adc2_bit_3 output digital output 2 <3>. 84 d16 adc2_bit_2 output digital output 2 <2>. 85 e15 adc2_bit_1 output digital output 2 <1>. 86 f15 adc2_bit_0 output digital output 2 <0> (lsb). 87 d15 adc2_clock input adc clock input. 88 c15 adc2_gndd supply digital gnd of adc circuitry. 89 d14 adc2_vddd supply digital supply of adc circuitry (nominal 2.5v). 90 b16 adc2_gnda supply analog gnd of adc circuitry. 91 b14 adc2_vdda supply analog supply of adc circuitry (nominal 2.5v). 92 c16 adc2_bit_inv input digital input. 0=no inve rsion of output bits; 1 = inversion of output bits. 93 a16 adc2_cmd_ss input biasing of second stage of adc. connect to v dda with r=50 k and decouple with c=100 nf to gnda. 94 b15 adc2_analog_in input analog input 2 nd adc. 95 a15 adc2_adc2_cmd_fs input analog reference inpu t. biasing of first stage of adc. connect to v dda with r=50 k and decouple with c=100 nf to gnda. 96 a14 adc2_ref_high input analog reference input. high reference voltage of adc. (see figure 9 for exact resistor value) 97 c14 vres_ds supply power supply reset drivers. 98 b13 vres supply power supply reset drivers. 99 a13 vmem_h supply power supply vmem drivers. 100 a9 vmem_l supply power supply vmem drivers. 101 a10 vpix supply power supply pixel array. 102 a11 reset input digital input. control of reset signal in the pixel. 103 a12 reset_ds input digital input. contr ol of double slope reset in the pixel. 104 b7 mem_hl input digital input. control of vmem signal in pixel. 105 b8 precharge input digital input. cont rol of vprecharge signal in pixel. 106 b9 sample input digital input. control of vsample signal in pixel. 107 b10 temp_diode_n testpin cathode of temperature diode. 108 b11 temp_diode_p testpin anode of temperature diode. table 16. pin list [6, 7, 8] (continued) pad pin pin name pin type description [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 25 of 31 109 b6 precharge_bias input analog reference input. biasing for pixel array. (see table 10 for exact resistor and ca pacitor value). 110 a8 photodiode testpin output photodiode. 111 a7 gndd ground ground digital modules. 112 b12 vdd supply power supply digital modules. 113 a6 eos_y_l testpin indicates when the end of fr ame is reached when scanning in the 'left' direction. 114 a1 sync_y input digital input. synchronises the y-address register. 115 a5 clock_y input digital input. clock of the y-addressing. 116 a2 norowsel input digital input. cont rol signal of the column readout. 117 a3 volt. averaging input digital input. control sign al of the voltage averaging in the column readout. 118 b5 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 119 a4 sh_col input digital input. control signal of the column readout. 120 b1 prebus2 input digital input. control signal to reduce readout time. 121 b2 prebus1 input digital input. control signal to reduce readout time. 122 c1 dec_y_load input analog reference input. biasing for y-addressing. 123 d1 vpix supply power supply pixel array. 124 b4 va3 supply power supply column modules. 125 b3 gnda ground ground analog modules. 126 c2 vaa supply power supply analog modules. 127 e2 gndd ground ground digital modules. table 16. pin list [6, 7, 8] (continued) pad pin pin name pin type description notes 6. all pins with the same name can be connected together. 7. all digital input are active high (unless mentioned otherwise). 8. all unused inputs should be tied to a non active level (for example, v dd or gnd). [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 26 of 31 package drawing figure 24. lupa 4000: 127 pin pga package drawing 001-07580 *a [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 27 of 31 bonding diagram the die is bonded to the bonding pads of the package as shown in figure 25 . additional package information die size: 25610 um x 27200 um cavity pad: 27000 um x 29007 um pixel 0,0 is located at 478 um from the left hand side of the die and 1366 um from the bottom side of the die. figure 25. bonding pads diagram of the lupa 4000 package 001-48359 ** [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 28 of 31 glass transmittance a d263 glass is used as protection glass lid on top of the lupa 4000 monochrome sensors. figure 26 shows the transmission characteristics of the d263 glass. figure 26. transmission characteristics of the d263 glass used for lupa 4000 sensors handling precautions and recommended storage conditions for proper handling and storage conditions, refer to cypress application note an52561 on www.cypress.com . limited warranty cypress image sensor business unit warrants that the image sensor products mentioned here, if properly used and serviced, conform to the seller's published specifications. they are free from defects in material and workmanship for one (1) year following the date of shipment. if a defect is identified within the one (1) year period, cypress will either replace the product or give credit for the product. 0 10 20 30 40 50 60 70 80 90 10 0 400 500 600 700 800 900 wavelength [nm] transmission [%] [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 29 of 31 appendix a: lupa 4000 evaluation system an lupa 4000 evaluation kit is available for evaluation purposes. this kit consists of a multifunctional digital board (memory, sequencer, and ethern et) and an analog image sensor board. bench tools software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all acquired images and movies can be stored in different file formats (8 or 16 bit). all setting can be adjusted on the fly to evaluate the sensors specifications. default register values can be loaded to start the software in a desired state. figure 27. contents of lupa 4000 evaluation kit for more information on image sensors, contact imagesensors@cypress.com . [+] feedback
cyil1sm4000aa document number: 38-05712 rev. *d page 30 of 31 appendix b: frequently asked questions q: how does the dual (multiple) slope extended dynamic range mode works? a: the green lines in figure 28 are the analog signal on the photodiode, which decrease as a result of exposure. the slope is determined by the amount of ligh t at each pixel (the more light the steeper the slope). when the pixels reach the saturation le vel the analog signal does not change despite further exposure. without any double slope, pulse pixels p3 and p4 reaches saturation bef ore the sample moment of the analog values, no signal is acquired without double slope. when double slope is enabled a second reset pulse is given (blue line) at a certain time before the end of the integration time. this double slope reset pulse resets the a nalog signal of the pixels below this level to the reset level. after the re set the analog signal starts to decrease with the same slope as before the double slope reset pulse. if the double slope reset pulse is placed at the end of the integration time (90% for instance) t he analog signal that reaches the saturation levels are not saturated an ymore (this increases the optica l dynamic range) at read out. not e that pixel signals above the double slope reset level are not influenced by this double slope reset pulse (p1 and p2). figure 28. dual slope diagram p4 p3 p2 p1 reset level 1 reset level 2 saturation level total integration time reset pulse double slope reset pulse read out d oubl e sl ope reset ti me ( usual l y 5- 10% of the total integrati on time) [+] feedback
document number: 38-05712 rev. *d revised september 18, 2009 page 31 of 31 all products and company names mentioned in this document may be the trademarks of their respective holders cyil1sm4000aa ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress offers standard and customized cmos image sensors for co nsumer as well as industrial and professional applications. consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelli gent traffic systems, security, and barcode applications. cypress's cust omized cmos image sensors are characterized by very high pix el counts, large area, very high frame rates, la rge dynamic range, a nd high sensitivity. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's representatives, and distributors. for more information on image sensors, please contact imagesensors@cypress.com . document title: cyil1sm4000aa lupa 4000: 4 megapixel cmos image sensor document number: 38-05712 rev. ecn no. orig. of change submission date description of change ** 310396 fpw see ecn initial cypress release *a 497132 qgs see ecn converted to frame file *b 649219 fpw see ecn ordering information up date+ title update + package spec label *c 2738057 nvea/pyrs 07/16/0 9 updated templa te, extensive content edits *d 2765859 nvea 09/18/09 updated ordering information table [+] feedback

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